One type of semiconductor package is referred to as a BGA package. BGA packages were developed to provide a higher lead count, and a smaller foot print, than conventional plastic or ceramic semiconductor packages. A BGA package includes an area array of solder balls that permit the package to be surface mounted to a printed circuit board (PCB) or other electronic component.
One type of prior art BGA package 10 is illustrated in FIG. 1A. The BGA package 10 includes a substrate 12, an array of solder balls 14 on the substrate 12, and a semiconductor die 16 on the substrate 12 in electrical communication with the solder balls 14. The BGA package 10 also includes a die encapsulant 18 that encapsulates the die 16, and a wire bond encapsulant 20 that encapsulates wire bonds 22 between the die 16 and a pattern of conductors 36 on the substrate 12. In addition, the BGA package 10 includes a solder mask 24 having openings 26 on selected areas of the conductors 36 wherein the solder balls 14 are located.
Typically the substrate 12 comprises a reinforced polymer laminate material, such as bismaleimide triazine (BT), or a polyimide resin. In addition, the substrate 12 is initially a segment of a substrate panel 12P (FIG. 2A) which is similar to a lead frame used in the fabrication of conventional plastic semiconductor packages. The substrate panel 12P includes multiple substrates 12, and is used to fabricate multiple BGA packages 10. Following the fabrication process for the BGA packages 10, the substrate panel 12P is singulated into individual BGA packages 10.
The die encapsulant 18 and the wire bond encapsulant 20 can comprise a plastic material such as a Novoloc based epoxy formed using transfer molding process. The BGA package 10 is sometimes referred to as being "asymmetrical" because the die encapsulant 18 has a larger size and volume than the wire bond encapsulant 20.
One problem with the asymmetrical BGA package 10, which is illustrated in FIGS. 1B and 1C, occurs during molding of the wire bond encapsulants 20. During fabrication of the BGA packages 10 on the substrate panel 12P, the die encapsulants 18 are initially molded to the substrate panel 12P using a first mold fixture 28 (FIG. 1B). The first mold fixture 28 includes mold cavities 30 (FIG. 1B) and associated runners (not shown) in flow communication with a source of heated, pressurized plastic. The mold cavities 30 are configured to mold the die encapsulants 18 onto the substrate panel 12P.
After molding the die encapsulants 18, the wire bond encapsulants 20 are molded to the panel 12P using a second mold fixture 32 (FIG. 1C). The second mold fixture 32 also includes mold cavities 34 (FIG. 1C) and associated runners (not shown) in flow communication with a source of heated, pressurized plastic. The mold cavities 34 are configured to mold the wire bond encapsulants 18 on the substrate panel 12P.
Because of the construction of the first mold fixture 28, a relatively high clamping pressure P1 (FIG. 1B) can be exerted on either side of the substrate panel 12P for sealing the mold cavities 30 during molding of the die encapsulants 18. However, because of the construction of the second mold fixture 32, only a relatively low clamping pressure P2 (FIG. 1B) can be exerted on one side of the panel 12P for sealing the mold cavities 34 during molding of the wire bond encapsulants 20.
The relatively low clamping pressure P2 can allow excess plastic material, or "flash", to escape from the mold cavities 34 (FIG. 1C). The flash can deposit on the conductors 36 (FIG. 1A), and in the openings 26 (FIG. 1A) in the solder mask 24 (FIG. 1A). Depending on its location, the flash can adversely affect the solder balls 14, and the bonded connections between the solder balls 14 and the conductors 36.
In view of the foregoing, improved methods for controlling mold flash during fabrication of semiconductor packages are needed in the art. The present invention is directed to a method for fabricating a semiconductor package in which mold flash is contained on a selected area of the package.